1. Field of the Invention
The present invention relates to an ion implantation method and semiconductor device manufacturing method using a batch processing ion implantation apparatus and relates particularly to an ion implantation method and semiconductor device manufacturing method by which variation in breakdown voltage of the well region boundary formed below an element isolation region is prevented.
2. Description of the Related Art
Ion implantation is extensively used in manufacturing semiconductor integrated circuits. Both N and P wells are generally created by ion implantation. Ion implantation is classified into two categories: the batch processing system and the single wafer processing system. In the batch processing system, impurity ions are implanted in multiple semiconductor substrates at a time. In the single wafer processing system, impurity ions are implanted in a single semiconductor substrate at a time. Thus, the ion implantation apparatus is classified into two types: the batch processing ion implantation apparatus and the single wafer processing ion implantation apparatus. They have different structures.
FIG. 13 is an illustration schematically showing a disc (a plate-shape support) provided in the batch processing ion implantation apparatus. As shown in FIG. 13, a disc 3 is rotatable about the disc rotation axis passing through the center 31 of the disc 3. Multiple semiconductor substrates 2 are mounted in an annular form around the rotation axis (center 31) of the disc 3.
For ion implantation, the disc 3 is rotated at a speed of 1,000 rpm or higher and an ion beam 1 is emitted to the disc 3. The ion beam 1 is a cluster of impurity ions accelerated in a specific direction (injection direction) to be implanted in the semiconductor substrates 2. In this type of ion implantation apparatus, the ion beam 1 is not scanned (deflected), having a fixed irradiation point. Therefore, impurity ions are implanted in the semiconductor substrates 2 when the semiconductor substrates 2 reach the irradiation point of the ion beam 1 while the disc 3 rotates. In FIG. 13, the ion beam 1 irradiates the semiconductor substrate 2 at the uppermost position in the figure.
The disc 3 is movable in a plane perpendicular to the ion beam 1 in a diameter direction of the disc 3. For example, in the ion implantation apparatus in which the ion beam 1 is emitted horizontally, the entire disc 3 can move vertically. Impurity ions are implanted uniformly in the entire surface of the semiconductor substrate 2 while the disc 3 rotates and linearly reciprocates across a diameter of the semiconductor substrate 2 in conjunction with the ion beam 1.
The batch processing ion implantation apparatus as described above is used for medium to large ion current (implantation dose rate) regions. More specifically, it is used for well implantation, drain extension implantation, high concentration impurity implantation in gate electrodes and high concentration impurity implantation for source and drain regions. The semiconductor substrates 2 in FIG. 13 have a notch 30 indicating a crystal surface orientation of the semiconductor substrate 2. In FIG. 13, the semiconductor substrates 2 are placed on the disc 3 with the notch 30 directed to the center 31, whereby the semiconductor substrates 2 are directed in the same manner when they reach the irradiation position of the ion beam 1.
On the other hand, FIG. 14 is an illustration schematically showing a relationship between the ion beam 1 and semiconductor substrate 2 during ion implantation in the single wafer processing ion implantation apparatus. In FIG. 14, the ion beam 1 is emitted horizontally. A single semiconductor substrate 2 is placed in the single wafer processing ion implantation apparatus shown in FIG. 14. The ion beam 1 is scanned on the semiconductor substrate 2 by the vertical magnetic field generated by magnets 41.
In the case of FIG. 14, the semiconductor substrate 2 is placed on a substrate support (not shown) that is movable in a diameter direction of the semiconductor substrate 2 (for example vertically). The horizontal scanning of the ion beam 1 and the vertical reciprocal movement of the semiconductor substrate 2 allow impurity ions to be implanted uniformly in the entire surface of the semiconductor substrate 2.
The single wafer processing ion implantation apparatus as described above is often used for small to medium ion current regions. More specifically, it is used for well implantation, pocket implantation for MOS transistor source and drain regions and implantation for threshold voltage control.
Generally, impurity ions implanted example in a single crystal silicon semiconductor substrate should be inhibited to reach deep inside the semiconductor substrate by channeling in the ion implantation process. To this end, the ion beam 1 is emitted at an angle in relation to the normal line of the surface of the semiconductor substrate 2. The semiconductor substrate 2 is held on the disc 3 or a substrate support in the manner that the ion beam 1 enters the semiconductor substrate 2 at an angle in relation to the normal line of the surface thereof in either type of ion implantation apparatus although this is not shown in detail in FIGS. 13 and 14.
In a conventional CMOS semiconductor integrated circuit device, the semiconductor substrate 2 has N and P wells. These wells are formed using the above described batch processing or single wafer processing ion implantation apparatus. In the up-to-date semiconductor integrated circuit device, MOS transistors are provided at a high density. The boundary between N and P wells is often formed in the semiconductor region below a fine element isolation region.
FIG. 15A is a cross-sectional view showing an ideal boundary between N and P wells (well boundary) formed in the semiconductor region below an element isolation region. In the case of FIG. 15A, the element isolation region has an STI (shallow trench isolation) structure consisting of an insulator such as a silicon oxide film embedded in a trench formed in the semiconductor substrate surface. In order to form a well boundary in the semiconductor region below an STI structure 26, a resist pattern 4 having an opening edge at the center 27 of the STI structure is used as an ion implantation mask as shown in FIG. 15A. In other words, for the ion implantation to form an N well 6, a resist pattern 4 having an opening above the region to be an N well 6 and the opening edge at the center 27 of the STI structure 26 is formed. As N type impurity ions are implanted using the resist pattern 4 as a mask, the ions partly pass through the STI structure 26 and form an N well 6 also in the semiconductor region below the STI structure 26. Similarly, in order to form a P well 7, P type impurity ions are implanted using as an ion implantation mask a resist pattern 5 having an opening above the region to be a P well 7 and the opening edge at the center 27 of the STI structure 26 as shown in FIG. 15B. In this way, the ions partly pass through the STI structure 26 and form a P well 7 also in the semiconductor region below the STI structure 26.
The N and P wells 6 and 7 formed as described above are symmetric about the center 27 of the STI structure 26. Consequently, the well boundary 10 is formed at the center 27 of the STI structure 26. The above well implantation is performed at a high implantation energy level that allows for transmission through the STI structure 26. Therefore, the N and P wells 6 and 7 are so-called retrograde wells with which the impurity concentration is higher in the inside than in the surface part of a semiconductor substrate.
This is the ideal well boundary. As described above, in the actual ion implantation, the ion beam 1 enters the semiconductor substrate 2 at an angle in relation to the normal line of the surface of the semiconductor surface 2. Therefore, when the N well forming resist pattern 4 is formed and the ion beam 1 is emitted for example in a direction tilted to the resist pattern 4, a part of the semiconductor region below the STI structure 26 is in the shadow of the resist pattern 4. In such a case, no N type impurity layer is formed in the semiconductor region in the shadow of the resist pattern 4 as an N well 6a shown in FIG. 15C. In this state, when P type impurity ions are implanted at the same injection angle as the ion beam 1 of FIG. 15C using the P well forming resist pattern 5 as a mask, a P well 7a is formed also in the semiconductor region below the resist pattern 5 as shown in FIG. 15D. In this case, the well boundary 10a is not formed at the center 27 of the STI structure 26.
Conversely, when the N well forming resist pattern 4 is formed and the ion beam 1 is emitted in a direction tilted away from the resist pattern 4, an N well 6b is formed also in the semiconductor region below the resist pattern 4 as shown in FIG. 15E. In this state, when P type impurity ions are implanted at the same injection angle as the ion beam 1 of FIG. 15E using the P well forming resist pattern 5 as a mask, a P well 7b is formed as shown in FIG. 15F; no P type semiconductor layer is formed in the semiconductor region in the shadow of the resist pattern 5. Also in this case, the well boundary 10b is not formed at the center 27 of the STI structure 26.
It is known that the ability of the well to isolate the elements or a well-to-well breakdown voltage of the well boundary is decreased when the well boundary is not formed at the center 27 of the STI structure 26. The decrease in the well-to-well breakdown voltage is more apparent as the width of the STI structure 26 (the transverse width of the STI structure in FIGS. 15A to 15F) is reduced.
In order to resolve the above problem, the Japanese Laid-Open Patent Publication No. 2002-26274 discloses a technique to prevent the decrease in the well-to-well breakdown voltage. FIGS. 16A to 16C are cross-sectional views showing the process of the ion implantation technique disclosed in the prior publication. In this technique, as shown in FIGS. 16A and 16B, the injection direction of an ion beam 11 for forming a P well 7 and the injection direction of an ion beam 12 for forming an N well 6 are opposite to each other about the center 27 of the STI structure 26. In such a case, as shown in FIG. 16C, the N well 6 and P well 7 nearly electrically compensate with each other in a region 13 where they overlap and the well boundary is formed substantially at the center 27 of the STI structure 26. Consequently, the decrease in the well-to-well breakdown voltage can be prevented. Furthermore, the prior publication proposes a technique in which ion implantation for forming a P well and ion implantation for forming an N well are each performed in four directions in a symmetric manner. Then, the dependency of the well-to-well breakdown voltage on the well boundary forming direction is reduced and a high well-to-well breakdown voltage can be obtained in any perpendicular directions on the semiconductor substrate.